An image data composed of two-dimensionally arrayed pixels is a set of a plurality of bits of pixel data. The pixel data may be composed of a luminance signal Y and color difference signals Cb, Cr, or may be composed of RGB gradation signals. Each signal generally consists of 8 bits (1 byte).
Now, with regard to the memory for storing the image data, for example a general-purpose memory such as SDRAM, the internal circuit thereof is composed of an 8-bit (1-byte) data unit. Therefore, the data bus width of the general-purpose memory is a multiple of 8 i.e. the bit length of the data unit, namely, 8 bits, 16 bits, 32 bits or 64 bits. In other words, in response to an address supplied from a memory controller, the general-purpose memory inputs and outputs data having the bit length in the above data bus width. As such, an area for storing data having the bit length selected by the address is referred to as a memory unit area. Accordingly, the memory unit area is composed of a multiple of 8 bits (1 byte) corresponding to the number of bits in the data bus width of the memory. Also, the data bus width, namely, the number of bits in the memory unit area corresponds to the bit length of one word.
In recent years, accompanying the enhancement of image quality, the pixel data has a bit length that exceeds 8 bits, such as 10 bits and 12 bits. In such pixel data of high image quality, the bit length thereof other than a multiple of 8 bits brings about an impediment to access efficiency to the general-purpose memory. For example, with regard to pixel data each consisting of 10 bits, it is necessary to handle 4 pixel data as data consisting of 5 bytes (8×5=40 bits). Incase that a bit length of one word, namely data bus width, is 32 bits, it is necessary to input and output 16 pixel data as data consisting of 5 words, by accessing the memory five times.
In the Japanese Unexamined Patent Publication No. 2005-32035, when storing, into a memory, data having a unit data bit length of 10 bits or 12 bits, which is not a multiple of 8, it is described that a second memory is used, or alternatively, data each consisting of 10 bits or 12 bits are stored into a single memory by successively packing the above data. For this purpose, a plurality of buffer registers are provided in a memory access circuit, and input data stored in the plurality of buffer registers are appropriately selected, so as to match with a memory data bus width.
In the Japanese Unexamined Patent Publication No. Hei-7-105638, it is described that, by dividing a 10-bit image data into an upper 8 bits and a lower 2 bits, the upper 8 bits are stored into a magnetic tape intact, while in regard to the lower 2 bits, 4 samples are packed to compose 8 bits, and after adding an error correction parity, the data is recorded into the magnetic tape. By this, it is explained that the image quality can be improved by means of error correction.